1. Field of the Invention
The present invention relates to an integrated circuit technique, and, more particularly, to a technique for resetting an integrated circuit. More specifically, the present invention relates to resetting an integrated circuit using a non-dedicated reset pin.
2. Description of Related Art
An integrated circuit is typically provided on a chip having a number of pins. A reset feature generally needs to be provided for the integrated circuit. One easy way to provide such a reset feature is to designate one of the chip pins as a dedicated reset pin. FIG. 1 shows an integrated circuit 100 according to the prior art. Integrated circuit has a number of pins 102, 104, 106, 108, 110, 112, 114, 116, 118, 120 and also a designated reset pin RESET. In one example, the designated reset pin RESET is toggled between a high value, which indicates that the chip is to reset, and a low value, which indicates the chip is to operate in a normal mode.
Lowering the pin count of a chip is generally desirable. For example, a lower pin count helps lower the manufacturing costs of a chip and may make the chip more marketable due to the lower number of pin interfaces. In lowering the pin count of a chip, the designated reset pin is often omitted. When the designated reset pin is omitted to reduce pin count, another way for resetting the chip needs to be provided.
One such alternative way for indicating chip reset is a power-on reset. A power-on reset generally involves the chip detecting whether a power supply voltage level at a power supply pin has exceeded a certain threshold. When the power supply voltage level has exceeded the certain threshold, then the chip has been powered on and the chip needs to be reset. Otherwise, the chip operates in the normal manner. However, the problem with a power-on reset is that the power supply may not have completely turned on or may not have been stable when it turned on. In these situations, the chip may not have reset at the appropriate time when the power-on occurred, which may cause the chip to cease operating or cause other operating errors. For testing of a chip, it is desirable to control the exact time of when the chip leaves reset, and such control is difficult to obtain with a power-on reset.
Thus, the present invention recognizes the desire and need for providing a way for resetting an integrated circuit without the use of a dedicated reset pin. The present invention further recognizes the desire and need to reset an integrated circuit, which avoids using a power-on reset. The present invention also recognizes the desire and need to provide a way for resetting an integrated circuit without adding additional pins. The present invention overcomes the problems and disadvantages in accordance with the prior art.